Barely one in four ASICs comes back right the first time. And that number is getting worse — through UVM, formal, emulation, and now AI.
Here’s the uncomfortable part nobody puts on a slide: almost everything we call “verification” tests an abstraction of your chip. Your UVM testbench runs against RTL. Your formal proofs run against RTL. Your emulator runs a transformed model of RTL.
Exactly one step in the whole flow tests the netlist you actually ship — with real resets, real X’s, and real timing annotated onto real gates. Gate-level simulation. The step every schedule review tries to kill first.
And I get why. GLS is slow, painful, and lands at the worst possible moment — the final weeks before tapeout, when everyone wants green dashboards. At 2nm, with the corner counts Apple and MediaTek are now signing off, it only gets uglier.
But after two decades of tapeouts, I’ve noticed something: teams don’t cut GLS because it stopped finding bugs. They cut it because it finds them at a time when nobody wants to hear it. That’s not a simulation problem. That’s a risk-management problem wearing a simulation costume.
GLS isn’t a tax on your schedule. It’s the cheapest silicon respin you’ll ever buy.
Over my next few posts I’ll break down where GLS still earns its cost — and where it’s become pure ritual.
Until then: what’s the last bug you caught only in GLS — and could anything else in your flow have caught it?