A classic high-speed SerDes failure mode:
The link looks perfect — until it slowly isn’t.
No CRC errors. No protocol violations. Yet after sustained traffic, the eye drifts, the sampling point moves, and BER creeps up. The data is correct, but the average signal level isn’t.
This is exactly the problem DC balancing was designed to solve.
On AC-coupled serial links, long-term bias in the data stream causes baseline wander. Coupling capacitors charge, thresholds shift, CDR margin erodes, and eventually the receiver fails. These are slow, history-dependent failures — and some of the hardest to catch in verification.
Early SerDes protocols solved this deterministically.
Encodings like 8b/10b (PCIe Gen1/2, SATA, Fibre Channel) tightly controlled running disparity. DC balance and transition density were guaranteed, at the cost of ~25% overhead.
As bandwidth pressure increased, efficiency won.
Protocols moved toward scrambling-based approaches:
PCIe Gen3-5: 128b/130b + scrambling
- Ethernet: 64b/66b + scrambling
- SATA Gen3+: scrambling
DC balance became statistical, not guaranteed. Receiver design absorbed more responsibility, and verification shifted from symbol legality to long-run behavior.
Modern links take different but related paths.
HDMI 2.1 / 2.2 (FRL mode): uses 16b/18b encoding, which explicitly improves DC balance and transition density compared to older TMDS, combined with scrambling at higher rates. This reflects HDMI’s need for strong electrical robustness over consumer-grade channels, while still improving efficiency.
PAM4 links (PCIe Gen6/7, 112G Ethernet): go even further — relying almost entirely on scrambling, fixed framing (FLITs/blocks), and very strong receiver signal processing (baseline wander compensation, offset cancellation, adaptive EQ). There is often no explicit DC-balancing code at all.
Across these protocols, the philosophy is converging.
The industry trend is clear:
DC balance has moved from “encoded in every symbol” to “managed by the entire link.”
For verification, that means:
Fewer deterministic DC checks
- More long-run and payload-dependent stress testing
- Greater reliance on mixed-signal assumptions
- Closer coupling between protocol behavior and analog receiver limits
At today’s SerDes speeds, DC balance isn’t a checkbox — it’s a system-level risk you actively manage.